This invention relates generally to digital systems and specifically to signal interference in digital systems.
In digital systems, data is typically sampled on the rising edge of a system clock, although in some systems data may be sampled on the falling edge of the clock (or even on both clock edges). FIG. 1 shows an ideal clock signal CLK_ideal having a period T. Associated data is sampled on each rising edge of CLK_ideal. As shown in FIG. 1, CLK_ideal is a clean signal having smooth transitions between logic low and high states, and thus data is sampled once per clock cycle.
In actual applications, however, signal interference (e.g., cross-talk, noise, ground bounce) may cause one or more undesirable glitches in the clock signal which may be erroneously detected as additional clock edges. These unintended clock edges cause inadvertent sampling of the data which, in turn, may lead to data errors.
For example, FIG. 2 shows a clock signal CLK_actual having associated signal interference that produces an unintended state transition within each rising edge. That is, rather than having a smooth rising edge from logic low to logic high, CLK_actual rises to a first level A, falls slightly to a second level B, and then rises again to a maximum level. Here, both the initial transition to level A and the subsequent transition to the maximum level may be interpreted as rising clock edges. The inadvertent state transition occurring after the rising edge of CLK_actual causes data to be sampled more than once per clock cycle, and thereby may result in data errors.
Unintended state transitions in the clock signal are typically filtered by using voltage hystersis to detect logic state transitions. Voltage hysteresis filters unwanted voltage transitions by using different thresholds for detecting rising and falling edges. For example, as shown in FIG. 2, a rising clock edge is detected when CLK_actual exceeds an upper threshold X, and a falling edge is detected when CLK_actual falls below a lower threshold Y. Thus, setting the hysteresis levels at X and Y filters undesirable voltage transitions in CLK_actual between levels X and Y.
Although hysteresis is effective in discriminating against unintended state transitions, controlling the upper and lower hysteresis levels over temperature and process variations is difficult, and typically requires complex circuitry such as, for instance, band-gap reference circuits and high-speed comparators. Further, the upper and lower hysteresis levels are usually set during circuit fabrication and, therefore, cannot later be changed to compensate for actual circuit performance and/or interference characteristics. In addition, although possible to implement a dynamic hysteresis that tracks circuit and signal interference characteristics, the feedback circuitry required to implement dynamic hysteresis is of a size and complexity which renders it impractical to independently implement for a large number of input/output (I/O) pins.
An apparatus and method are disclosed that discriminate against signal interference over temperature and process variations without consuming significant silicon area. In accordance with one embodiment of the present invention, a clock signal is monitored to detect a transition from a first logic state to a second logic state. Once this transition is detected, subsequent transitions of the clock signal are ignored for a predetermined time period during which signal interference may be most significant. After lapse of the predetermined time period, the clock signal is again monitored to detect subsequent state transitions. In some embodiments, the clock signal is delayed using a delay circuit to produce a delayed clock signal, and the clock signal and the delayed clock signal are logically combined to determine the predetermined time period. In one embodiment, the predetermined time period is user-selectable via one or more taps on the delay circuit.